1. Field of the Invention
This invention relates generally to digital signal processing and, more specifically, to the efficient use of memory and/or logic resources in implementing functions such as multi-channel integrators and multi-channel differentiators used in multi-channel decimators, multi-channel interpolators, multi-channel numerically controlled oscillators (NCOs) and similar structures and/or functions in programmable or otherwise configurable devices, including programmable logic devices.
2. Description of Related Art
A programmable logic device (“PLD”) is a programmable integrated circuit (IC) that allows the user of the circuit, using software control, to program the PLD to perform particular logic functions. A wide variety of these devices are manufactured by Altera Corporation of San Jose, Calif. For the purpose of this description, it is to be understood that a programmable logic device refers to once programmable as well as re-programmable devices. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not been capable of performing any specific function until after it has been configured by a user.
Therefore, a user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, programs the PLD to perform a particular function or a plurality of functions required by the user's application. Configuration data, such as a bitstream, can be sent to the PLD to program and/or configure the PLD to perform one or more desired functions. This programming of a PLD uses various device resources, including logic elements (LEs), that are found on a given programmable device.
Many digital signal processing devices use multi-channel integrators and/or differentiators. For example, such structures may be used in decimation units to condition data. Decimation (or down-sampling) of a signal reduces the number of data points in the original data signal, typically to permit use of the data at a lower data rate. Decimation is used in a variety of digital signal processing devices in a wide range of applications (for example, medical imaging).
Multi-channel cascaded integrator-comb (CIC) filters are used frequently in digital modulation and demodulation circuits. Often, such uses involve interpolation and/or decimation, in which the data signal is digitally up-sampled or down-sampled, respectively. Proper conditioning of a signal as part of a data rate change is critical to proper digital signal processing. Moreover, multi-channel integrators and differentiators may be used in wireless systems that need to handle multiple channels of voice and/or data.
Basic single channel CIC filters are shown in FIGS. 1A and 1B. As seen in the Figures, CIC filters can be used for both decimation and interpolation. In a CIC filter used for decimation, as seen in FIG. 1A, the unit 110 includes an integrator unit 112, followed by a down-sampler 114, followed by a differentiator unit 116. Similarly, a CIC filter used for interpolation has a unit 120 using a differentiator unit 122, an up-sampler 124 and an integrator unit 126. The up-sampler and down-sampler blocks are simple to implement in a programmable device, such as a PLD, as will be appreciated by those skilled in the art. Moreover, these blocks do not utilize substantial programmable device resources.
A standard prior art single channel, 5 stage integrator unit 140 is shown in FIG. 1C. Integrator section 140 consists of five integrators 142 that each have an adder 144 and a delay element 146 using a feedback line 148, configured in a manner known to those skilled in the art. A standard prior art single channel, 5 stage differentiator section 150 is shown in FIG. 1D. Differentiator unit 150 consists of five differentiators 152, each having a subtractor 154 and a delay element 156 using a feedforward line 158, again configured in a manner known to those skilled in the art. CIC filters typically require such multiple stages and thus take up significant device resources when multiple channels are supported. Typical wireless applications, for example, may need as many as five stages to support the filter requirements of such systems.
FIG. 2 shows circuitry for a unit such as the one shown in FIG. 1A using prior art techniques for implementing a 5 stage, 8 channel CIC filter for decimation in a programmable device. As seen in FIG. 2, circuit 200 has 8 input lines 210a, 210b, 210c, 210d, 210e, 210f, 210g and 210h, each of which handles one channel's data. Line 210a inputs data to an integrator unit 220 consisting of five individual integrators 222. Each integrator 222 is made up of an adder 224, an associated delay element 226 and a feedback line 228 in a standard configuration. The output of one line's integrator unit 220 is input into that channel's own down-sampler 230, where the data rate is reduced. The output of each channel's down-sampler 230 is then input into a differentiator unit 240 consisting of five individual differentiators 242. Each differentiator 242 is made up of a subtractor 244, an associated delay element 246 and a feedforward line 248 in a standard configuration.
Each stage may contain data busses greater than 64 bits to handle the dynamic range of the filter. If, for example, 8 channels are needed for decimation and the data bus is 64 bits, then the required resources (in terms of logic elements) for the integrator and differentiator sections of the circuit of FIG. 2 are:((64*5)int+(64*5*2)diff)*8=7680LEs
In a situation where 16 channels are needed with each supporting data widths of 50 bits, with a 5 stage CIC, then the following LE resources are needed:
Integrator—50*16*5=4000 LEs
Differentiator—50*16*5*2=8000 LEs
Total—12000 LEs
As seen in Table 1, the number of required LEs for standard 5 stage CIC filtering schemes increases proportionally with the implementation of additional channels. The following table shows results for 64 bit data and 5 stage CIC filters:
TABLE 1NumberLEs required usingof channelscurrent CIC implementation876801615360242304032307206461440128122880
NCOs also use structures that are essentially identical to the integrators of CIC type filters and devices. An NCO generates sinusoidal signals of a desired frequency for various functions and purposes in programmable devices. A standard, single channel NCO 300 is shown in FIG. 3A. A phase incrementation value is input at the NCO input 302 and is used in a phase accumulator 304, which is basically a single stage integrator. The phase accumulator rotates the angular position of a phasor about the unit circle at a rate defined by the input phase increment. A polar-to-cartesian transformation of the phase value that is output from the phase accumulator is performed by a sine and cosine generation unit 306 to yield the output sinusoidal values.
As seen in FIG. 3B, a prior multi-channel NCO 300 implemented on a digital device 301 (for example, a PLD) generates sine and cosine values for multiple channels in a device. An N channel system has N NCOs 303a, 303b, . . . , 303N using inputs 302a, 302b, . . . , 302N to generate N pairs of sine and cosine values, one pair corresponding to each frequency generated by a channel's phase accumulator 304. As with integrators and differentiators used for CIC filtering, current implementations of multi-channel NCOs in programmable devices and the like require substantial device resources in terms of LE usage.
Systems, methods and techniques that permit implementation of various multi-channel integrators and multi-channel differentiators for use in CIC filters, NCOs and the like that can support multiple channels of data, while efficiently using area, speed and other resources in a PLD or other digital signal processing device would represent a significant advancement in the art. Moreover, generating a flexible, standard structure to implement a variety of CIC filters, NCOs and the like whose rates can be adjusted easily would likewise constitute a significant advancement in the art.